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february 2004 1 document control # ml0023 rev 0.3 stk17ta8 nvtime ? event data recorder 128k x 8 autostore ?nvsram with real-time clock product preview features ? data integrity of simtek nvsram combined with full-featured real-time clock ? 25ns, 35ns and 45ns access times ? software or autostore ? store to quan- tumtrap ? nonvolatile elements ? recall to sram initiated by software or power restore ? unlimited read, write and recall cycles ? 100-year data retention ? watchdog timer ? clock alarm with programmable interrupts ? capacitor or battery backup for rtc ? single 3v +20%, -10% operation ? commercial and industrial temperatures ? packages: 48 pin ssop, 40 pin dip description the simtek stk17ta8 combines a 1 mbit nonvola- tile static ram with a full- featured real-time clock in a reliable, monolithic integr ated circuit. the embed- ded nonvolatile elements incorporate simtek?s quantumtrap ? technology producing the world?s most reliable nonvolatile memory. the sram can be read and written an unlimited number of times, while independent, nonvolatile data resides in the nonvol- atile elements. the real-time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. the alarm function is pro- grammable for one-time alarms or periodic seconds, minutes, hours, or days. there is also a programma- ble watchdog timer for process control. block diagram quantum trap 1024 x 1024 store recall column i/o column dec static ram array 1024 x 1024 input buffers store/ recall control power control dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 software detect a 0 - a 16 g e w rtc mux a 0 - a 16 row decoder a 5 a 6 a 7 a 8 a 9 a 12 a 13 a 14 a 15 a 16 a 0 a 1 a 2 a 3 a 4 a 10 a 11 v ccx v cap hsb int x 2 x 1 v rtcbat v rtccap
stk17ta8 february 2004 2 document control # ml0023 rev 0.3 packages pin descriptions pin name i/o description a 0 - a 16 input address: the 17 address inputs se lect one of 131,072 bytes in the nvsram array or one of 16 bytes in the clock register map. dq 0 -dq 7 i/o data: bi-directional 8-bit data bus for accessing the nvsram array and clock. e input chip enable: the active low e input selects the device. w input write enable: the active low w enables data on the dq pins to be written to the adddress location latched by the falling edge of e . g input output enable: the active low g input enables the data output buffers during read cycles. deasserting g high causes the dq pins to tri-state. x 1 , x 2 input crystal: connections for 32.768 khz crystal. v rtccap power supply capacitor supplied backup rtc supply voltage. v rtcbat power supply battery supplied backup rtc supply voltage. v ccx power supply power (+ 3v) hsb i/o hardware store busy (i/o) int output interrupt output: can be programmed to respond to the clock alarm, the watchdog timer and the power monitor. programmable to either active high (push/pull) or active low (open-drain). v cap power supply autostore capacitor: supplies power to nvsram during power loss to store data from sram to nonvolatile elements. v ss power supply ground 48 pin 300 mil ssop 40 pin 600 mil dip (not to scale)
stk17ta8 february 2004 3 document control # ml0023 rev 0.3 dc characteristics (v cc = 3.0v + 20%, -10%) e note b: i cc 1 and i cc 3 are dependent on output loading and cycle rate. the specified values are obtained with outputs unloaded. note c: i cc 2 and i cc 4 are the average currents required for the duration of the respective store cycles (t store ). note d: e v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. note e: v cc reference levels throughout this datasheet refer to v ccx . ac test conditions capacitance f (t a = 25 c, f = 1.0mhz) note f: these parameters are guaranteed but not tested. symbol parameter commercial industrial units notes min max min max i cc 1 b average v cc current 70 60 55 75 65 60 ma ma ma t avav = 25ns t avav = 35ns t avav = 45ns i cc 2 c average v cc current during store 1 1 ma all inputs don?t care, v cc = max i cc 3 b average v cc current at t avav = 200ns 3v, 25c, typical 55ma w (v cc ? 0.2v) all others cycling, cmos levels i cc 4 c average v cap current during autostore ? cycle 0.5 0.5 ma all inputs don?t care i sb d v cc standby current (standby, stable cmos input levels) 0.3 0.3 ma e (v cc ? 0.2v) all others v in 0.2v or (v cc ? 0.2v) i ilk input leakage current 1 1 a v cc = max v in = v ss to v cc i olk off-state output leakage current 1 1 a v cc = max v in = v ss to v cc , e or g v ih i bak rtc backup current 200 300 na v bak rtc backup voltage 1.6 1.6 v v ih input logic ?1? voltage 2.0 v cc + .3 2.0 v cc + .3 v all inputs v il input logic ?0? voltage v ss ? .5 0.8 v ss ? .5 0.8 v all inputs v oh output logic ?1? voltage 2.4 2.4 v i out = ? 2ma v ol output logic ?0? voltage 0.4 0.4 v i out = 4ma t a operating temperature 0 70 ? 40 85 c input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 3v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns input and output timing reference levels . . . . . . . . . . . . . . . 1.5v output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see figure 1 symbol parameter max units conditions c in input capacitance 5 pf ? v = 0 to 3v c out output capacitance 7 pf ? v = 0 to 3v absolute maximum ratings a power supply voltage . . . . . . . . . . . . . . . . . . . . . . . .?0.5v to +3.9v voltage on input relative to v ss . . . . . . . . . . ?0.5v to (v cc + 0.5v) voltage on dq 0-7 . . . . . . . . . . . . . . . . . . . . . . ?0.5v to (v cc + 0.5v) temperature under bias . . . . . . . . . . . . . . . . . . . . . ?55 c to 125 c storage temperature. . . . . . . . . . . . . . . . . . . . . . . . ?65 c to 150 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1w dc output current (1 output at a time, 1s duration) . . . . . . . . 15ma note a: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at con- ditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability. 577 ohms 30 pf 789 ohms 3.0v including scope and output fixture figure 1: ac output loading
stk17ta8 february 2004 4 document control # ml0023 rev 0.3 sram read cycles #1 & #2 (v cc = 3.0v +20%, -10%) e note g: w must be high during sram read cycles. note h: device is continuously selected with e and g both low. note i: measured 200mv from steady state output voltage. sram read cycle #1: address controlled g , h sram read cycle #2: e controlled g no. symbols parameter stk17ta8-25 stk17ta8-35 stk17ta8-45 units #1, #2 alt. minmaxminmaxminmax 1t elqv t acs chip enable access time 25 35 45 ns 2t avav g t rc read cycle time 25 35 45 ns 3t avqv h t aa address access time 25 35 45 ns 4t glqv t oe output enable to data valid 10 15 20 ns 5t axqx h t oh output hold after address change 3 3 3 ns 6t elqx t lz chip enable to output active 3 3 3 ns 7t ehqz i t hz chip disable to output inactive 10 13 15 ns 8t glqx t olz output enable to output active 0 0 0 ns 9t ghqz i t ohz output disable to output inactive 10 13 15 ns 10 t elicch f t pa chip enable to power active 0 0 0 ns 11 t ehiccl f t ps chip disable to power standby 25 35 45 ns data valid 5 t axqx 3 t avqv dq (data out) address 2 t avav 6 t elqx standby data valid 4 t glqv dq (data out) e address 2 t avav g i cc active 10 t elicch 1 1 t ehiccl 7 t ehqz 8 t glqx 1 t elqv 9 t ghqz
stk17ta8 february 2004 5 document control # ml0023 rev 0.3 sram write cycles #1 & #2 (v cc = 3.0v + 20%, -10%) e note j: if w is low when e goes low, the outputs remain in the high-impedance state. note k: e or w must be v ih during address transitions. note l: hsb must be high during sram write cycles. sram write cycle #1: w controlled k, l sram write cycle #2: e controlled k, l no. symbols parameter stk17ta8-25 stk17ta8-35 stk17ta8-45 units #1 #2 alt. min max min max min max 12 t avav t avav t wc write cycle time 25 35 45 ns 13 t wlwh t wleh t wp write pulse width 20 25 30 ns 14 t elwh t eleh t cw chip enable to end of write 20 25 30 ns 15 t dvwh t dveh t dw data set-up to end of write 10 12 15 ns 16 t whdx t ehdx t dh data hold after end of write 0 0 0 ns 17 t avwh t aveh t aw address set-up to end of write 20 25 30 ns 18 t avwl t avel t as address set-up to start of write 0 0 0 ns 19 t whax t ehax t wr address hold after end of write 0 0 0 ns 20 t wlqz i, j t wz write enable to output disable 10 13 15 ns 21 t whqx t ow output active after end of write 3 3 3 ns previous data data out e address 12 t avav w 16 t whdx data in 19 t whax 13 t wlwh 18 t avwl 17 t avwh data valid 20 t wlqz 15 t dvwh high impedance 21 t whqx 14 t elwh data in 12 t avav 16 t ehdx 13 t wleh 19 t ehax 18 t avel 17 t aveh data valid 15 t dveh high impedance 14 t eleh data out e address w data in
stk17ta8 february 2004 6 document control # ml0023 rev 0.3 mode selection note m: the six consecutive addresses must be in the order listed. w must be high during all six consecutive cycles to enable a nonvolatile cycle. note n: while there are 17 addresses on the stk17ta8, only the lower 16 are used to control software modes. note o: i/o state depends on the state of g . the i/o table shown assumes g low. e w g a 15 - a 0 (hex) mode i/o power notes h x x x not selected output high z standby l h l x read sram output data active l l x x write sram input data active lhl 4e38 b1c7 83e0 7c1f 703f 8b45 read sram read sram read sram read sram read sram autostore inhibit output data output data output data output data output data output data active m, n, o lhl 4e38 b1c7 83e0 7c1f 703f 4b46 read sram read sram read sram read sram read sram autostore inhibit off output data output data output data output data output data output data active m, n, o lhl 4e38 b1c7 83e0 7c1f 703f 8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active l cc 2 m, n, o lhl 4e38 b1c7 83e0 7c1f 703f 4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active m, n, o
stk17ta8 february 2004 7 document control # ml0023 rev 0.3 autostore ?/power-up recall (v cc = 3.0v + 20%, -10%) e note p: t restore starts from the time v cc rises above v switch . note q: if an sram write has not taken place since the last nonvolatile cycle, no store will take place. autostore ?/power-up recall no. symbols parameter stk17ta8 units notes standard alternate min max 22 t restore power-up recall duration 5 ms p 23 t store t hlhz store cycle duration 10 ms q 24 v switch low voltage trigger level 2.55 2.65 v power-up recall brown out no store (no sram writes) brown out autostore ? brown out autostore ? recall when v cc returns above v switch autostore ? w 22 t restore power-up recall 24 v switch v cc dq (data out) 23 t store
stk17ta8 february 2004 8 document control # ml0023 rev 0.3 software-controlled store / recall cycle s (v cc = 3.0v + 20%, -10%) e note r: the software sequence is clocked with e controlled reads or g controlled reads. note s: the six consecutive addresses must be in the order listed in the hardware mode selection table: (4e38, b1c7, 83e0, 7c1f, 703f, 8fc0) for a store cycle or (4e38, b1c7, 83e0, 7c1f, 703f, 4c63) for a recall cycle. w must be high during all six consecutive cycles. software store / recall cycle: e controlled s software store / recall cycle: g controlled s no. symbols parameter stk17ta8-25 stk17ta8-35 stk17ta8-45 units notes e cont g cont alternate min max min max min max 25 t avav t avav t rc store / recall initiation cycle time 25 35 45 ns s 26 t avel t avgl t as address set-up time 0 0 0 ns 27 t eleh t glgh t cw clock pulse width 20 25 30 ns 28 t elax t glax address hold time 20 20 20 ns 29 t recall t recall recall duration 20 20 20 s data valid high impedance address #6 address #1 data valid 25 t avav data valid dq (data) e address 23 29 t store / t recall 25 t avav 26 t avel 27 t eleh 28 t elax g data valid high impedance address #6 address #1 data valid 25 t avav data valid e address 23 29 t store / t recall 25 t avav 26 t avgl 27 t glgh 28 t glax g dq (data)
stk17ta8 february 2004 9 document control # ml0023 rev 0.3 hardware store cycle t (v cc = 3.0v + 20%, -10%) e note t: t recover is only applicable after t store is complete. hardware store cycle no. symbols parameter stk17ta8 units notes standard alternate min max 30 t store t hlhz store cycle duration 10 ms i 31 t delay t hlqz time allowed to complete sram cycle 1 si 32 t recover t hhqx hardware store high to inhibit off 100 ns t 33 t hlhx hardware store pulse width 15 ns 34 t hlbl hardware store low to store busy 300 ns data valid hsb (in) data valid 33 t hlhx 31 t delay 30 t store 32 t recover high impedance 34 t hlbl high impedance dq (data out) hsb (out)
stk17ta8 february 2004 10 document control # ml0023 rev 0.3 nvsram the stk17ta8 has two separate modes of opera- tion: sram mode and nonvolatile mode. in sram mode, the memory opera tes as a standard fast static ram . in nonvolatile mode, data is transferred from sram to the nonvolatile elements (the store operation) or from the nonvolatile elements to sram (the recall operation). in this mode sram func- tions are disabled. the stk17ta8 supports unlim- ited reads and writes to the sram, unlimited recalls from the nonvolatile elements and up to 1 million stores to the nonvolatile elements sram read the stk17ta8 performs a read cycle whenever e and g are low and w is high. the address specified on pins a 0-16 determines which of the 131,072 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t avqv ( read cycle #1). if the read is initiated by e or g , the outputs will be valid at t elqv or at t glqv , whichever is later ( read cycle #2). the data outputs will repeatedly respond to address changes within the t avqv access time without the need for tran- sitions on any control input pins, and will remain valid until another address change or until e or g is brought high, or w is brought low. sram write a write cycle is performed whenever e and w are low. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at th e end of the cycle. the data on the common i/o pins dq 0-7 will be writ- ten into the memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write . it is recommended that g be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if g is left low, internal circuitry will turn off the output buffers t wlqz after w goes low. autostore ? operation the stk17ta8 can be powered in one of three modes. during normal operation, the stk17ta8 will draw current from v ccx to charge a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. after power up, when the voltage on the v ccx pin drops below v switch , the part will autom atically disconnect the v cap pin from v ccx and initiate a store opera- tion. figure 2 shows the proper connection of capacitors for automatic store opera tion. a charge storage capacitor having a capacity of between 10 f and 100 f ( 20%) rated at minimum of 5v should be provided. in order to prevent unneeded store operations, automatic store s as well as those initiated by externally driving hsb low, will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initi- ated store cycles are performed regardless of whether a write operation has taken place. hsb can be used to signal the system that the autostore ? cycle is in progress. hsb operation the stk17ta8 provides the hsb pin for controlling and acknowledging the store operations. the hsb pin can be used to request a hardware store cycle. when the hsb pin is driven low, the stk17ta8 will conditionally initiate a store operation after t delay ; an actual store cycle will only begin if a write to the sram took place since the last store or figure 2: autostore ? mode if hsb is not used it should be left uncon nected vcap vss vccx 10 f 5v, 20% 0.1 f bypass + 10k ? 10k ?? w device operation
stk17ta8 february 2004 11 document control # ml0023 rev 0.3 recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the stk17ta8 will continue sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it will be allowed a time, t delay , to complete. however, any sram write cycles requested after hsb goes low will be inhibited until hsb returns high. the hsb pin can be used to synchronize one stk17ta8 with one or more stk14ca8 nvsrams to expand the memory space. to operate in this mode the hsb pins from each device should be connected together. an exter nal pull-up resistor to + 3.0v is required since hsb acts as an open drain pull down. the v cap pins from the other parts can be tied together and share a single capacitor. the capacitor size must be scaled by the number of devices connected to it. when any one of the devices detects a power loss and asserts hsb , the common hsb pin will cause all parts to request a store cycle (a store will take place in those devices that have been written since the last nonvol- atile cycle). during any store operation, regardless of how it was initiated, the stk17ta8 will continue to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation the stk17ta8 will remain disabled until the hsb pin returns high. if hsb is not used, it should be left unconnected. power-up recall during power up, or after any low-power condition (v ccx < v switch ), an internal recall request will be latched. when v cap once again exceeds the sense voltage of v switch , a recall cycle will automatically be initiated and will take t restore to complete. if the stk17ta8 is in a write state at the end of power-up recall , the write will be inhibited and e or w must be brought high and then low for a write to initiate. software nonvolatile store the stk17ta8 software store cycle is initiated by executing sequential e controlled read cycles from six specific address locations. during the store cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvol- atile elements. the program operation copies the sram data into nonvolatile memory. once a store cycle is initiated, further input and output are dis- abled until the cycle is completed. because a sequence of read s from specific addresses is used for store initiation, it is impor- tant that no other read or write accesses inter- vene in the sequence, or the sequence will be aborted and no store or recall will take place. to initiate the software store cycle, the following read sequence must be performed: 1. read address 4e38 (hex) valid read 2. read address b1c7 (hex) valid read 3. read address 83e0 (hex) valid read 4. read address 7c1f (hex) valid read 5. read address 703f (hex) valid read 6. read address 8fc0 (hex) initiate store cycle the software sequence may be clocked with e con- trolled read s or g controlled read s. once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be disabled. it is important that read cycles and not write cycles be used in the sequence, although it is not necessary that g be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. software nonvolatile recall a software recall cycle is initiated with a sequence of read operations in a manner similar to the soft- ware store initiation. to initiate the recall cycle, the following sequence of e controlled read opera- tions must be performed: 1. read address 4e38 (hex) valid read 2. read address b1c7 (hex) valid read 3. read address 83e0 (hex) valid read 4. read address 7c1f (hex) valid read 5. read address 703f (hex) valid read 6. read address 4c63 (hex) initiate recall cycle internally, recall is a two-step procedure. first, the sram data is cleared, and second, the nonvolatile
stk17ta8 february 2004 12 document control # ml0023 rev 0.3 information is transferred into the sram cells. after the t recall cycle time the sram will once again be ready for read and write operations. the recall operation in no way alters the data in the nonvolatile elements. preventing stores the autostore ? function can be disabled by initiat- ing an autostore inhibit sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore inihibit sequence, the following sequence of e controlled read operations must be performed: 1. read address 4e38 (hex) valid read 2. read address b1c7 (hex) valid read 3. read address 83e0 (hex) valid read 4. read address 7c1f (hex) valid read 5. read address 703f (hex) valid read 6. read address 8b45 (hex) autostore inhibit the autostore inhibit can be disabled by initiating an autostore inhibit off sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore inhibit off sequence, the following sequence of e controlled read operations must be performed: 1. read address 4e38 (hex) valid read 2. read address b1c7 (hex) valid read 3. read address 83e0 (hex) valid read 4. read address 7c1f (hex) valid read 5. read address 703f (hex) valid read 6. read address 4b46 (hex) autostore inhibit off the last autostore inhibit state is stored in nonvola- tile memory and is retained through power cycling. noise considerations the stk17ta8 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 f connected between v cap and v ss , using leads and traces that are as short as pos- sible. as with all high-speed cmos ics, normal care- ful routing of power, ground and signals will help prevent noise problems. hardware write protect the stk17ta8 offers hardware protection against inadvertent store operation and sram write s dur- ing low-voltage conditions. when v ccx < v switch , all externally initiated store operations and sram write s will be inhibited. low average active power the stk17ta8 draws significantly less current when it is cycled at times longer than 50ns. figure 3 shows the relationship between i cc and read cycle time. worst-case current consumption is shown for commercial temperature range, v cc = 3.6v, and 100% duty cycle on chip ena ble. figure 4 shows the same relationship for write cycles. if the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. the overall average current drawn by the stk17ta8 depends on the fo llowing items: 1) the duty cycle of chip enable; 2) the overall cycle rate for accesses; 3) the ratio of read s to write s; 4) the operating temperature; 5) the v cc level; and 6) i/o loading. figure 3: i cc (max) reads figure 4: i cc (max) writes 0 10 20 30 40 50 50 100 150 200 cycle time (ns) average active current (ma) 0 10 20 30 40 50 50 100 150 200 cycle time (ns) average active current (ma)
stk17ta8 february 2004 13 document control # ml0023 rev 0.3 nvtime operation the stk17ta8 offers internal registers that contain clock, alarm, watchdog, inte rrupt, and control func- tions. internal double buffering of the clock and the clock/timer information registers prevents accessing transitional internal clock data during a read or write operation. double buffering also circumvents dis- rupting normal timing coun ts or clock accuracy of the internal clock while accessing clock data. clock and alarm registers store data in bcd format. clock operations the clock registers maintain time up to 9,999 years in one second increments. the user can set the time to any calendar time and the clock automatically keeps track of days of the week and month, leap years and century transitions. there are eight regis- ters dedicated to the clock functions which are used to set time with a write cycl e and to read time during a read cycle. these registers contain the time of day in bcd format. bits defined as ?x? are currently not used and are reserved for future use by simtek. reading the clock while the double-buffered rtc register structure reduces the chance of readi ng incorrect data from the clock, the user should halt internal updates to the stk17ta8 clock registers before reading clock data to prevent the reading of data in transition. stopping the internal register updates does not affect clock accuracy. the updating process is stopped by writing a ?1? to the read bit (in the control register 1fff0h), and will not restart until a ?0? is wr itten to the read bit. the rtc registers can then be read while the internal clock continues to run. within 10 msec after a ?0? is written to the read bit, all stk17ta8 registers are simultaneously updated. setting the clock setting the write bit (in t he control register 1fff0h) to a ?1? halts updates to the stk17ta8 registers. the correct day, date and time can then be written into the registers in 24-hour bcd format. resetting the write bit to ?0? transfers those values to the actual clock counters, afte r which the clock resumes normal operation. backup power the stk17ta8 is intended for permanently pow- ered operation, but when primary power, vcc, fails and drops below vswitch the device will switch to backup power from either vbakcap or vbakbat, depending on whether a capacitor or battery is cho- sen for the application. the clock oscillator uses ve ry little current, which maximizes the backup time available from the backup source. regardless of clock operation with the primary source remo ved, the data stored in vsram is secure, having been stored in the nonvol- atile elements as power was lost. factors to be con- sidered when choosing a backup power source include: the expected duration of power outages and the cost tradeoff of using a battery versus a capaci- tor. during backup operation the stk17ta8 consumes a maximum of 300 nanoamps at 2 volts. capacitor or battery values should be chosen according to the application. backup time values based on maximum current specs are shown below. nominal times are approximately 3 times longer. using a capacitor has the obvious advantage of recharging the backup sour ce each time the system is powered up. if a battery is used a 3v lithium is recommended and the stk17ta8 will only source current from the bat- tery when the primary power is removed. the bat- tery will not, however, be recharged at any time by the stk17ta8. the battery capacity should be cho- sen for total anticipated cumulative down-time required over the life of the system. stopping and starting the oscil- lator the oscillator may be stopped at any time. this fea- ture may be used to save battery or capacitor energy during long-term storage to increase shelf life. setting the oscen bit in register 1fff8h to 1 halts the oscillator. setting the bit to 0 enables the oscillator. the rtc does not run until the oscillator capacitor value backup time 0.1 f 72 hours 0.47 f 14 days 1.0 f 30 days
stk17ta8 february 2004 14 document control # ml0023 rev 0.3 is enabled. calibrating the clock the rtc is driven by a quartz controlled oscillator with a nominal frequency of 32.768 khz. clock accuracy will depend on the quality of the crystal, usually specified to 35 ppm limits at 25 c. this error could equate to + 1.53 minutes pe r month. the stk17ta8 employs a calibration circuit that can improve the accuracy to + 1/-2 ppm at 25 c. the calibration circuit adds or subtracts counts from the oscillator divider circuit. the number of times pulses are suppressed (sub- tracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in control register 1fff8h. adding counts speeds the clock up; subtracting counts slows the clock down. the calibration bits occupy the the five lower order bits in the control register 8. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit, where a ?1? indicates positive calibration and a ?0? indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscil- lator cycles. if a binary ?1? is loaded into the register, only the first 2 minutes of the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore each calibration step has the effect of adding 512 or subtracti ng 256 oscillator cycles for every 125,829,120 actual o scillator cycles. that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. in order to determine how to set the calibration one may set the cal bit in register 1fff0h to 1, which causes the int pin to toggle at a nominal 512 hz. any deviation measured from the 512 hz will indi- cate the degree and direction of the required correc- tion. for example, a reading of 512.010124 hz would indicate a +20 ppm error, requiring a -10 (001010) to be loaded into the calibration register. note that setting or changing the calibration register does not affect the frequency test output frequency. alarm the alarm function compares user-programmed val- ues to the corresponding time-of-day values. when a match occurs, the alarm event occurs. the alarm drives an internal flag, af, and may drive the int pin if desired. there are four alarm match fields. they are date, hours, minutes and seconds. each of these fields also has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field will be used in the match process. depending on the match bits, the alarm can occur as specifically as one particular second on one day of the month, or as frequently as once per second continuously. the msb of each alarm register is a match bit. selecting none of the match bits (all 1?s) indicates that no match is required. the alarm occurs every second. setting the match select bit for seconds to ?0? causes th e logic to match the sec- onds alarm value to the current time of day. since a match will occur for only one value per minute, the alarm occurs once per minute. likewise, setting the seconds and minutes match bits causes an exact match of these values. thus, an alarm will occur once per hour. setting seconds, minutes and hours causes a match once per day. lastly, selecting all match values causes an exact time and date match. selecting other bit combinations will not produce meaningful results, however the alarm circuit should follow the functions described. there are two ways a user can detect an alarm event, by reading the af flag or monitoring the int pin. the af flag in the register 1fff0h will indicate that a date/time match has occurred. the af bit will be set to 1 when a match occurs. reading the flags/control register clears the alarm flag bit (and all others). a hardware interrupt pin may also be used to detect an alarm event. watchdog timer the watchdog timer is a free running down counter that uses the 32 hz clo ck (31.25 ms) derived from the crystal oscillator. the oscillator must be running for the watchdog to function. it begins counting down from the value loaded in the watchdog timer register. the counter consists of a loadable register and a free running counter. on power up, the watchdog timeout value in register 1fff7h is loaded into the
stk17ta8 february 2004 15 document control # ml0023 rev 0.3 counter load register. counting begins on power up and restarts from the loadable value any time the watchdog strobe (wds) bit is set to 1. the counter is compared to the terminal value of 0. if the counter reaches this value, it causes an internal flag and an optional interrupt output. the user can prevent the timeout interrupt by setting wds bit to 1 prior to the counter reaching 0. this causes the counter to be reloaded with the watchdog timeout value and to be restarted. as long as the user sets the wds bit prior to the counter reaching the terminal value, the inter- rupt and flag never occurs. new timeout values can be written by setting the watchdog write bit to 0. when the wdw is 0 (from the previous operation), ne w writes to the watchdog timeout value bits d5-d0 allow the timeout value to be modified. when wdw is a 1, then writes to bits d5-d0 will be ignored. the wdw function allows a user to set the wds bit without concern that the watchdog timer value will be modified. a logical dia- gram of the watchdog timer is shown below. note that setting the watchdog timeout value to 0 would be otherwise meaningless and therefore disables the watchdog function. the output of the watchdog timer is a flag bit wdf that is set if the watchdog is allowed to timeout. the flag is set upon a watchdog timeout and cleared when the flags/control regist er is read by the user. the user can also enable an optional interrupt source to drive the int pin if the watchdog timeout occurs. power monitor the stk17ta8 provides a power management scheme with power-fail interrupt capability. it also controls the internal switch to backup power for the clock and protects the memory from low-vcc access. the power monitor is based on an internal band-gap reference circuit that compares the vcc voltage to various thresholds. as descibed in the autostore ? section previously, when vswitch is reached as vcc decays from power loss, a data store operatio n is initiated from sram to the nonvolatile elements, securing the last sram data state. power is also switched from vccx to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source no data may be read or written and the clock functions are not available to the user. the clock continues to operate in the background. updated clock data is available to the user 10 msec after vcc has been restored to the device. interrupts the stk17ta8 provides three potential interrupt sources. they include the watchdog timer, the power monitor, and the clock/calendar alarm. each can be individually enabled and assigned to drive the int pin. in addition, each has an associated flag bit that the host processor can use to determine the cause of the interrupt. some of the sources have additional control bits that determine functional behavior. in addition, the pin driver has three bits that specify its behavior when an interrupt occurs. a functional diagram of the interrupt logic is shown below. the three interrupts each have a source and an enable. both the source and the enable must be active (true high) in order to generate an interrupt figure 5. watchdog timer block diagram figure 6. interrupt block diagram
stk17ta8 february 2004 16 document control # ml0023 rev 0.3 output. only one source is necessary to drive the pin. the user can identify the source by reading the flags/control register, which contains the flags associated with each source. all flags are cleared to 0 when the register is read. the cycle must be a complete read cycle (we high); otherwise the flags will not be cleared. the power monitor has two pro- grammable settings that are explained in the power monitor section. once an interrupt source is active, the pin driver determines the behavior of the output. it has two programmable settings as shown below. pin driver control bits are located in the interrupts register. according to the programming selections, the pin can be driven in the backup mode for an alarm inter- rupt. in addition, the pin can be an active low (open- drain) or an active high (push-pull) driver. if pro- grammed for operation during backup mode, it can only be active low. lastly, the pin can provide a one- shot function so that the active condition is a pulse or a level condition. in one-shot mode, the pulse width is internally fixed at approximately 200 ms. this mode is intended to reset a host microcontrol- ler. in level mode, the pin goes to its active polarity until the flags/control regi ster is read by the user. this mode is intended to be used as an interrupt to a host microcontroller. the control bits are summa- rized as follows: watchdog interrupt enable - wie. when set to 1, the watchdog timer drives the int pin as well as an internal flag when a watchdog timeout occurs. whenwie is set to 0, the watchdog timer affects only the internal flag. alarm interrupt enable - ai e. when set to 1, the alarm match drives the int pin as well as an internal fla. when set to 0, the alarm match only affects to internal flag. power fail interrupt enable - pfe. when set to 1, the power fail monitor drives the pin as well as an internal flag. when set to 0, the power fail monitor affects only the internal flag. alarm battery-backup enabl e - abe. when set to 1, the clock alarm interrupt (as controlled by aie) will function even in battery backup mode. when set to 0, the alarm will occur only when vcc>vswitch. aie should only be set when the int pin is programmed for active low operation. in addition, it only functions with the clock alarm, not the watchdog. if enabled, the power monitor will drive the interrupt during all normal vcc conditions regardless of the abe bit. the application for abe is intended for power con- trol, where the system powers up at a predeter- mined time. depending on the application, it may require dedicating the int pin to this function. high/low - h/l. when set to a 1, the int pin is active high and the driver mode is push-pull. the int pin can drive high only when vcc>vswitch. when set to a 0, the int pin is active low and the drive mode is open-drain. active low (open drain) is operational even in battery backup mode. pulse/level - p/l. when set to a 1 and an interrupt occurs, the int pin is driven for approximately 200 ms. when p/l is set to a 0, the int pin is driven high or low (determined by h/l) until the flags/control register is read. when an enabled interrupt source activates the int pin, as external host can read the flags/control reg- ister to determine the cause. remember that all flags will be cleared when the register is read. if the int pin is programmed for level mode, then the condition will clear and the int pin will return to its inactive state. if the pin is programmed for pulse mode, then reading the flag also will clear the flag and the pin. the pulse will not complete its specified duration if the flags/control register is read. if the int pin is used as a host reset, then the flags/con- trol register cannot be read during a reset. during a power-on reset with no battery, the inter- rupt register is automatically loaded with the value 24h. this causes power-fail interrupt to be enabled with an active-low pulse.
stk17ta8 february 2004 17 document control # ml0023 rev 0.3 rtc register map x - resevered for future use * - not bcd values register map detail register bcd data function/range d7 d6 d5 d4 d3 d2 d1 d0 1ffffh 10 years years years: 00 - 99 1fffeh x x x 10s months months months: 01 - 12 1fffdh x x 10s day of month day of month day of month:01 - 31 1fffch xxxxx day of week day of week:01 - 07 1fffbh x x 10s hours hours hours: 00 - 23 1fffah x 10s minutes minutes minutes: 00 - 59 1fff9h x 10s seconds seconds seconds: 00 - 59 1fff8h oscen x cal sign calibration calibration values* 1fff7h wds wdw wdt watchdog* 1fff6h wie aie pfe abe h/l p/l x x interrupts* 1fff5h m x 10s alarm date alarm date alarm, day of the month: 01-31 1fff4h m x 10s alarm hours alarm hours alarm, hours: 00-23 1fff3h m 10 alarm minutes alarm minutes alarm, minutes: 00-59 1fff2h m 10 alarm seconds alarm seconds alarm, seconds: 00-59 1fff1h 10s centuries centuries centuries: 00 - 99 1fff0h wdf af pf x x cal w r flags* 1ffffh timekeeping - years d7 d6 d5 d4 d3 d2 d1 d0 10 years years contains the lower two bcd digits of the year. lower nibble contains the value for years; upper nibble contains the value for 1 0s of years. each nibble operates from 0 to 9. the range for the register is 0-99. 1fffeh timekeeping - months d7 d6 d5 d4 d3 d2 d1 d0 x x x 10s months months contains the bcd digits of the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble ( one bit) c ontains the upper digit and operates from 0 to 1. the range for the register is 1-12. 1fffdh timekeeping - date d7 d6 d5 d4 d3 d2 d1 d0 x x 10s day of month day of month contains the bcd digits for the date of the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. the range for the register is 1-31.
stk17ta8 february 2004 18 document control # ml0023 rev 0.3 1fffch timekeeping - day d7 d6 d5 d4 d3 d2 d1 d0 xxxxxday of week lower nibble contains a value that correlates to day of the week. day of the week is a ring counter that counts from 1 to 7 the n returns to 1. the user must assign meanting to the day value, as the day is not integrated with the date. 1fffbh timekeeping - hours d7 d6 d5 d4 d3 d2 d1 d0 12/24 x 10s hours hours contains the bcd value of hours in 24 hour format. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the range for the register is 0-23. 1fffah timekeeping - minutes d7 d6 d5 d4 d3 d2 d1 d0 x 10s minutes minutes contains the bcd value of minutes. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the up per min- utes digit and operates from 0 to 5. the range for the register is 0-59. 1fff9h timekeeping - seconds d7 d6 d5 d4 d3 d2 d1 d0 x 10s seconds seconds contains the bcd value of seconds. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the up per digit and operates from 0 to 5. the range for the register is 0-59. 1fff8h contol/calibration d7 d6 d5 d4 d3 d2 d1 d0 oscen x calibration sign calibration oscen oscillator enable. when set to 1, the osc illator is halted. when set to 0, the o scillator runs. disabling the oscillator saves battery/capacitor power during storage. on a no-battery power-up, this bit is set to 1. the rtc will not run until the oscillator is enabled. set this bit to 0 to activate the rtc. calibration sign determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base. calibration these five bits control the calibration of the clock. 1fff7h watchdog timer d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to 1 reloads and restarts the watchdog timer. setting the bit to 0 has no affect. the bit is cleared automat- ically once the watchdog timer is reset. the wds bit is write only. reading it always will return a 0. wdw watchdog write enable. setting this bit to 1 masks the watchdog ti meout value (wdt5-wdt0) so it ca nnot be written. this allows the user to strobe the watchdg without disturbing the timeout value. setting this bit to 0 allows bits 5-0 to be witten on the next writ e to the watchdog register. the new value will be loaded on the nex internal watchdog clock after the writ e cycle is complete. this function is e xplained in more detail in the watchdog timer section.
stk17ta8 february 2004 19 document control # ml0023 rev 0.3 wdt watchdog timeout selection. the watchdog timer interval is selected by the 6-bit value in this register. it represents a multip lier of the 32 hz count (31.25 ms). the minimum range or timeout value is 31.25 ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3fh). setting the watchdog timer register to 0 disables the timer. these bits can be written only if the wdw bit was cleared to 0 on a previous cycle. 1fff6h interrupt status/control d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfe abe h/l p/l xx wie watchdog interrupt enable. when set to 1 and a watchdog timeout occurs, the watchdog timer drives the int pin as well as the wd f flag. when set to 0, the watchdog timeout affects only the wdf flag. aie alarm interrup enable. when set to 1, the alarm match drives the in t pin as well as the af flag. when set to 0, the alarm match only affects the af flag. pfe power-fail enable. when set to 1, the alarm match drives the int pin as well as the af flag. when set to 0, the power-fail moni tor affects only the pf flag. abe alarm battery-backup enable. when set to 1, the alarm interrupt (as controlled by aie) will function even in battery backup mod e. when set to 0, the alarm will occur only when vcc>vswitch. h/l high/low. when set to a 1, the int pin is driven active hi gh. when set to 0, the int pin is open drain, active low. p/l pulse/level. when set to a 1, the int pin is driven active (determined by h/l) by an interrupt source for approximately 200 ms. when set to a 0, the int pin is driven to an active level (as set by h/l) until the flags/control register is read. 1fff5h alarm - day d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm date alarm date contains the alarm value for the date of the month and the mask bit to select or deselect the date value. m match. setting this bit to 0 causes the date value to be used in the alarm match. setting this bit to 1 causes the match circui t to ignore the date value. 1fff4h alarm - hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm hours alarm hours contains the alarm value for the hours and the mask bit to select or deselect the hours value. m match. setting this bit to 0 causes the hours value to be used in the alarm match. setting this bit to 1 causes the match circu it to ignore the hours value. 1fff3h alarm - minutes d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm minutes alarm minutes contains the alarm value for the minutes and the ma sk bit to select or deselect the minutes value m match. setting this bit to 0 causes the minutes value to be used in the alarm match. setting this bit to 1 causes the match cir cuit to ignore the minutes value. 1fff2h alarm - seconds d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm seconds alarm seconds contains the alarm value for the seconds and the ma sk bit to select or deselect the seconds value 1fff7h watchdog timer d7 d6 d5 d4 d3 d2 d1 d0
stk17ta8 february 2004 20 document control # ml0023 rev 0.3 m match. setting this bit to 0 causes the seconds value to be used in the alarm match. setting this bit to 1 causes the match cir cuit to ignore the seconds value. 1fff1h timekeeping - centuries d7 d6 d5 d4 d3 d2 d1 d0 x x 10s centuries centuries 1fff0h flags d7 d6 d5 d4 d3 d2 d1 d0 wdf af pf x x cal w r wdf watchdog timer flag. this read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the us er. it is cleared to 0 when the flags/control register is read. af alarm flag. this read-only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. it is cleared when the flags/control register is read. pf power-fail flag. this read-only bit is set to 1 when power falls below the power-fail threshold vswitch. it is cleared to 0 whe n the flags/con- trol register is read. cal calibration mode. when set to 1, the clock enters calibration mode. when set to 0, the clock operates normally. w write time. setting the w bit to 1 freezes updates of the timekeeping registers. the user can then write them with updated valu es. setting the w bit to 0 causes the contents of the time registers to be transferred to the timekeeping counters. r read time. setting the r bit to 1 copies a static image of the timekeeping registers and places them in a holding register. the user can then read them without concerns over chan ging values causing system errors. the r bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again. 1fff2h alarm - seconds d7 d6 d5 d4 d3 d2 d1 d0
stk17ta8 february 2004 21 document control # ml0023 rev 0.3 ordering information temperature range blank = commercial (0 to 70c) i = industrial (-40 to 85c) access time 25 = 25ns 35 = 35ns 45 = 45ns lead finish blank = 85%sn/15%pb f = 100% sn (matte tin) package r = plastic 48-pin 300 mil ssop w = plastic 40-pin 600 mil dip stk17ta8 - r f 45 i
stk17ta8 february 2004 22 document control # ml0023 rev 0.3 document revision history revision date summary 0.0 february 2003 publish new datasheet 0.1 march 2003 remove 525 mil soic, add 48 pin ssop and 40 pin dip packages; modified block dia- gram in autostore description section 0.2 june 2003 modify 600 mil dip pinout (switch pins 32 and 33), update power-up recall specs, update software controlled store/recall cycle, added hardware store description, modified mode selection table, updated vswitch, updated t store , modify i bak and v bak 0.3 february 2004 change part number from stk17c a8 to stk17ta8; add lead-free finish option

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